Decimal data-handling equipment

ABSTRACT

An arrangement for adding together two n-digit decimal numbers or subtracting one n-digit decimal number from another comprises 10-condition switch means, the 10 conditions corresponding respectively to digits in the range 0 to 9 to be added or subtracted, and means to determine the need for and to implement the necessary carries.

References Cited Kamoi UNITED STATES PATENTS 4/1963 Harford........................ 2/1967 Bray.......

Primary Examiner-Malcolm A. Morrison Assistant Examiner-R. Stephen Dildine, Jr.

Attorney-Fleit, Gipple & Jacobson ABSTRACT: An arrangement for adding together two n-digit decimal numbers or subtracting one n-digit decimal number from another comprises IO-condition switch means, the 10 conditions corresponding respectively to digits in the range 0 to 9 to be added or subtracted, and means to determine the need for and to implement the necessary carries.

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L 0 a v 4 O BARRY NB PLAT BR Arthur L. Whitwell ll Watt Road, llillington, Glasgow, S.W. 2, Scotland Appl. No. 773,089

Nov. 4, I968 [45] Patented July 20, 1971 [32] Priority Nov. 7, 1967 [33] Great Britain 16 Claims, 14 Drawing Figs.

United States Patent [72] Inventor 22 Filed [54] DECIMAL DATA-HANDLING EQUIPMENT s1 [50] FicldofSearch.....

0R BATE cam CARRY PATENTED JUL20 197i sum 1 or 6 aun SHIFISWHEH ADDED SHIFT mun m1 em m an 15 OUTPUT T0 mun smn SWITCH 13 .1 NE] CARRY UR BATE INPUT m u l I 17 l l 0R GATE [AR RY INPUT'TU DISH SHIFT SWITIZH AnflUrCHu SH Fr-r DI PATENTED 1111201911 5 94.561,

SHEET 2 OF 6 n 110 CARRY Mi AND AND AND AND AND AND 5; AND AND 1111 DATE JUMP ND CARRY CARRY CARRN PATENTEU JUL20 I97! SHEET 5 0F 6 IJEEUUER FIGJO.

CUKJ QJZAUMJQU- 2 0\UJB755L3 UIFUI 1 OUTPUT TU [110R SHIFT SWITEH FIG .72.

SHIFT mun INPUT 10 mm smn swnm T' T' T T T T .T T T T [1R GATE UR BATE FIG .73.

BARRY AND AND

SH FT UI PATENTEDJUL20|97| 3594.561

SHEET 5 BF 6 INPUT O O O O 0R GATE 0R BMW JUMP CARRY NU CARRY CARRY DECIMAL DATA-HANDLING EQUIPMENT BACKGIROUND'OF THE INVENTION This invention relates to decimaL-data-handling equipment, and more particularly to arrangements for shifting the value of a decimal number, for example by adding to it another decimal number of fixed but arbitrary value.

In thefield of digital electronic computers many circuits and methods have been developed for performing arithmetic operations such as addition, subtraction and multiplication. The circuits and methods employed have been almost exclusively based on binary, binary coded decimal, or some other code based on binary numbers. By comparison, straightforward representations of decimal numbers have rarely been investigated because of the problems inherent in carrying out a multiplicity of successive arithmetic operations on them.

More recently, however, interestin digital methods of computing has extended to digital measurements for the online control of processes or machines. In applications of this type, a human operator may be a necessary'link in the sequence of control or measurement and hence representations of various parameters such as displacements may be required in decimal notation as this is the form most readily understood by the.

any discontinuity of supplies therefore introduced errors into the system and reference to the datum had to be made to remove such errors. However, an absolute system is described in National Engineering Laboratory report No. 233, entitled An Absolute Digital Measuring System using Optical Grating and Shaft Encoder," by A. Russell.

It may be necessary with an absolute system of this kind to have some means of comparing positional information with information relating to a reference position, and this means may comprise an arrangement for adding together two decimal numbers.

SUMMARY OF THE INVENTION According to the present invention, an arrangement for addingtogether two n-digit decimal numbers, comprises:

1. for each decade of the numbers except that corresponding to the least significant digit;

first-means to add one to the input digit to. the decade if a digit and a further series of planes wired so as to cooperate with associated logic elements to generate a carry signal when required.

Alternatively, the means of comparing positional information with information relating to a reference position may comprise an arrangement for subtracting one decimal number from another.

According to another aspect of the present invention therefore, an arrangement for subtracting one n-digit decimal number from another comprises:

l. for each decade of the numbers except that corresponding to the least significant digit;

first means to subtract one from the input digit to the decade ifa carry signal is being supplied from the immediately preceding decade,

2. for each decade of the numbers;

second means to shift the input digit (after the subtraction of the carry if any) to a value equal to the least significant digit of the number obtained by differencing the input digit (after i the subtraction of the carry if any) and the digit to be subcarry signal is being supplied from the immediately preceding decade,

2. for each decade of the numbers;

second means to shift the input digit (after the addition of the carry if any) to a value equal to the least significant digit of the number obtained by summing the input digit (after the addition of the carry if any) and the digit to be added, the second means comprising IO-condition switch means, the t0 conditions corresponding respectively to digits in the range 0 to 9 to be added, 7

third means to generate a carry signal for the immediately succeeding decade when said addition or shift makes such a carry necessary, and

3. for all the decades of the numbers in common;

fourth means to generate a carry signal for the second succeeding decade when a carry signal is being generated for the immediately succeeding decade and the input digit to said immediately succeeding decade is 9.

Preferably said switch means is a multiplane switch having a first series of planes wired to perform said shift of the input BRIEF DESCRIPTION OF THE DRAWINGS Two arrangements in accordance with the present invention will now be described by way of example with reference to the accompanying drawings, in which:

' FIG. 1 is a table referred to in explaining the operation of the first arrangement.

FIG. 2 shows schematically a logic arrangement forming .part of the first arrangement,

FIGS. 3 and 4 show schematically logic arrangements referred to in explaining the operation of the first arrangement,

. FIG. 5 shows part of the first arrangement schematically,

FIG. 6 is a simplified schematic version of FIG. 5.

FIG. 7 shows the first arrangement in simplified schematic form,

FIG. 8 shows a modified version of part of the first arrangement and a series of truth tables,

FIG. 9 shows a further modification of part of the arrangement,

FIG. 10 is a table referred to in explaining the operation of the second arrangement,

FIG. 11 shows schematically a logic arrangement forming part of the second arrangement,

FIGS. 12 and 13 show schematically logic arrangements referred to in explaining the operation of the second arrangement, and

FIG. 14 shows part of the second arrangement schematically.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The first arrangement is particularly, but by no means exclusively, suitable for use in an absolute system of measurement for angular or linear displacement using decimal notation. As mentioned above, in such systems it is frequently necessary to have some means of comparing present positional information with information relating to a reference position, and this is conveniently done by the arrangement to be described.

Before describing the first arrangement it is convenient to consider the nature of the problem, and then a solution based on the use of logic elements.

Suppose then that it is required to add together two six'digit decimal numbers N, and N,,. N, being of fixed but arbitrary value. Furthermore, let the individual decimal digits of N be N,,N,,N,,N,.N and N.(ON 9), sothat N, canbe written N,N,N;N,N,N,.

N may be represented by a set of 10 outputs of a register or decoder, the outputs being numbered to 9. The value of each digit is represented by the presence l or absence (0) of a voltage or current on the appropriate output, so that if N,=3 15,670 it will be represented as follows:

Decoder outputs I The approach to summing N, and N x is as follows. The least significant digit (n OF N can have any value in the range 0 to 9 and as a result of the addition of the least significant digit of N, may be required to be reset to any other value in this range; all possible combinations being illustrated by the table of FIG. 1. For any particular shift, the least significant digit in the required output will vary through the sequence 0 to 9, the changeover 9 to 0 stepping back progressively as the number shift is increased. A carry of l to the next higher decade, that is to the digit represented by N is necessary for all the resultants below the diagonal line in the table.

One way in which the requirements for a carry may be summarized is as follows:

Let the individual digits of N, and N, be referred to generally as n, and n,. A carry is required for all n,+n, 9, which may be expressed:

5 11,59; 5 n,$9; (all combinations) (2) 5 $n, 9; ln,4; (some combinations) (3) No other combinations require a carry within a single decade.

The required summation may therefore be regarded as a shift (by a value equal to the appropriate digit of N in each of the digits of N,, plus provision for making carries as necessary. Three of the requirements for the arrangement are therefore:

1. A method of achieving stepwise rotation of the connections inputs, this being achieved in the arrangement to be described by providing a lO-pole IO-condition digit shift (some combinations) l) bined in an OR-gate 20, the output of which is connected to a two-input AND-gate 21. Inputs corresponding to an added shift digit of 5, 6, 7, 8 or 9 are supplied to another AND-gate 22 the output of which is connected to the other input of the gate 21. It will be seen that any combination of input signals to the gates 20 and 22 will result in the gate 21 supplying a signal to the carry line 14 (FIG. 2) of the next decade as required by expression 2).

The requirements for a carry signal in the case of expressions (l) and (3) are similar, and a logic arrangement corresponding to expression (1) only will therefore now be described with reference to H0. 4. The arrangement comprises a four-input OR-gate 30, a three-input QR-gate 3l and a two-input OR-gate 32, the output of the gates'30to 32 being connected to one input of each of three two-input ANDgates 33 to 35 respectively. The output of gates 33 to 35 together with the output of a further two-input AND-gate 36 are connected to the carry line 14 (FIG. 2).

A signal corresponding to an added shift digit 6 is supplied to the gate 30, signals corresponding to an added shift digit 7 are supplied to the gates 30 and 31, signals corresponding to an added shift digit 8 are supplied to the gates 30 to 32 and signals corresponding to an added shift digit 9 are supplied to the gates 30 to 32 and 36. The other inputs of gates 33 to 36 are connected to the inputs of the digit shift switch corresponding to digits 1 to 4 respectively. This arrangement results in a signal to the carry line 14 (FIG. 2), whenever the required combination of input signals is present, for example, if 3 and 8 are present simultaneously, the gate 34 will supply the output.

Reference will now be made to FIG. 5 which shows that part of the complete arrangement which deals with one decade. Provision for adding the carries is made in the way described above with reference to FIG. 2. Thus terminal 10 corresponding to input digit 0 is connected to AND-gates l1 and 12, the other inputs of which are connected to a no carry line 13 and a carry line 14 respectively. Further similar pairs of AND-gates are provided for each of the other inputs from the decoder I corresponding to digits 1 to 9.

' and the output of the gate 12 is connected to terminal 16 switch for each decade of the output from the decoder. 2.

Logic for determining the need for and creating a carry signal to the next decade when required. 3. Means for adding the carry 1 to the absolute digit represented by the input to any decade, except the decade corresponding to the least significant digit in N,

FIG. 2, to which reference is now made, shows the way in which the carry is added. Each of the inputs, for example the input tenninal 10 corresponding to digit 0, is connected to a pair of two-input AND-gates 11 and 12. The other inputs of the gates 11 and 12 are connected to a no carry line 13 and a carry line 14 respectively, the lines 13 and 14 being connected in a manner to be described later to the preceding decade. The output of the gage 11 is connected to a terminal 15 which forms the digit 0 input terminal for the lO-condition switch, and the output of the gate 12 is connected to the terminal 16 which forms the digit 1 input terminal for the IO-condition switch. Thus a signal applied to the terminal 10 will result in an output signal at the terminal 15 if there is no carry and an output at the terminal [6 if there is a carry. The required carry is therefore added, and a similar arrangement results in the addition of required carries to the other outputs of the decoder.

The method of providing a signal for the carry line 14, will now be described first with reference to FIG. 3. This figure shows a logic arrangement for providing a carry signal for the which forms the digit 1 input terminal for the switch 40.

The switch 40 has in fact got 15 planes, the first to 10th of which are used to perform the basic digit shift operation. Associated with these 10 planes are a group of 10 movable contacts 41 which are ganged together so that they can be positioned to contact the terminals corresponding to any one of the 10 digit input terminals. It will be seen that if the contacts 41 are brought to the position corresponding to the digit 1 input terminal 16, then the digits corresponding to the signals derived from the gates ll, 12 etc., will be shifted by 1 prior to being supplied to the output. Other shifts are achieved by appropriate settings of the contacts 41.

The method of deriving the carry signal to be supplied to the succeeding decade is similar in principle to that described above with reference to FlGS. 3 and 4, but is in fact achieved by the addition of a further 5 planes to the switch 40. The l lth to 14th planes are wired such that connections extend from the outputs of the 16 AND-gates corresponding to digits 1 to 4 and 6 to 9 to terminals in these planes as shown. Signals corresponding to digits 5 to 9 are also supplied to an OR-gate 42, the output of which is connected to terminals in the 15th plane as shown.

Associated with the l lth to 15th planes of the switch 40 are five movable contacts 43 which are ganged to the movable contacts 41. On selecting the digit shift by positioning the contacts 41, therefore, the contacts 43 will be moved to appropriate positions, and there are set up paths which correspond in function to the logic arrangements described above with reference to FIGS. 3 and 4, these paths operating so that when there is an appropriate combination of digits, such as to require a carry to the next decade, a signal is supplied to one input of the two-input OR-gate 44. The paths from the con tacts 43 associated with the I 1th to 14th planes include diodes 45 so as to avoid short-circuiting the input lines. The presence of an output from the gate 44 signifies the need for a carry to be supplied to the next decade. The output of the gate 44 is therefore supplied, by way of a transistor inverting or buffer amplifier 46, 47, to the no carry or carry line 13 or 14 of the next decade.

One further refinement of the arrangement is necessary to deal with a situation which has not previously been referred to. This is where carries are required simultaneously for two or more decades. This situation occurs wherever the sum of N, and N leads to two or more adjacent zeros on the resultant number. For example: 999 +1; 998 +2; etc. In such a situation the arrangement as described so far would miss the jump" carries and would in fact, for example, sum 999 +1 as 900, because no carry would be generated between 99 and 100.

That part of the arrangement shown in FIG. 5 is shown in very much simplified schematic form in FIG. 6; incoming carry signals appearing at the right-hand side and outgoing carry signals to the next succeeding decade appearing at the left-hand side. This same schematic arrangement is used in FIG. 7 to which reference is now made and which shows the complete arrangement. In this FIG. S S S and S, are standard digit shift switches in accordance with FIG. 5, whilst S (for N the most significant digit) does not require the output circuits and S (for N the least significant digit) does not require the input carry circuits so the input AND-gates are omitted.

A carry from a single digit shift on the least significant digit N of N to the next but one digit N, is only necessary when both N and N, are initially 9. That part of the arrangement already described will operate to provide a carry from the shift switch 40 for N thus changing the state of N, from 9 to 0. At this stage there is no zero shift setting on N so no carry will be generated within the switch circuit for the next decade. This signal is therefore derived externally by an AND-gate 50, which generates a carry to the decade corresponding to N, only when there is a carry out of the decade corresponding to N together with a signal on the zero input line to the shift switch in the decade corresponding to N (after the preceding carry). Similarly, a carry to the decade corresponding to the N will occur only when there is a carry signal into the decade corresponding to N and a signal on the zero input line to the decade corresponding to N, This completes the arrangement which therefore operates as described to sum decimal numbers.

A number of modifications may be made to the first arran'gement without departing from the invention, and some of these will now be briefly mentioned.

In the report referred to above, a method of interpolating a cyclic wave form such as a sine wave or serrisoid is described. One complete cycle represents a fixed displacement interval and decimal division is achieved by generating a family of five related functions with their zerocrossing points successively separated in 36 steps. The crossing points are sensed by level detectors providing 5 outputs which may be defined as A, B, C, D, and F. each output being capable of indicating only two possible states. Thus A present will be represented hereafter as A, and A absent will be represented hereafter as A.

In order to derive a complete decimal decode from these states the complement states A, E 5, and E are necessary, whereupon the following decimal code applies:

In some applications it may be desired to sum the two decimal numbers whilst the input or variable number is in the encoded state. To do this the first l0 planes of the shift switch 40 of FIG. 5 are wired as indicated in FIG. 8, the basis of this wiring being derived by the truth tables set out in that figure.

This arrangement provides for the basic digit switch, and it is now necessary to consider the provision for deriving a carry signal when required. It may be noted that any set of the encoded numbers, irrespective of the fixed digit shift, is cyclic, and the coded pairs representing digits 0 to 4 are the complement of the coded pairs representing digits 5 to 9. It follows that a carry can in fact be derived by an operation on the five primary output levels A to E although, as confirmed by the truth table corresponding to +1 of FIG. 8, it is necessary to complement E. In this case the jump carry is derived by connecting the switch inputs A and to an AND-gate 60 as shown in FIG. 8.

FIG. 9, to which reference is now made, shows a suitable circuit. The position of the five ganged switches 61 (which can conveniently be solid-state switches such as diode gates) is determined by whether or not there is a carry from the preceding decade. The positions shown correspond to the case where a carry is present. For the purpose of complementing E the inverter 62 is provided, but it is to be noted that although this additional inverter 62 is required, the number of AND-gates required for implementing the carry is only 10, as compared with 20 in the previously described arrangement. A similar method of deriving a carry signal may also be used when the digit shift is carried out on a decoded decimal output.

A further alternative circuit arrangement will now be briefly mentioned. As already stated, for any particular digit shift through the whole range 0 to 9, the resulting coded sequence of digits 0 to 4 is the complement of the sequence 5 to 9. It follows therefore, that only five planes are absolutely necessary on the shift switch, and it would be possible to perform the operations previously carried out by the remaining five planes, by providing inverters to derive the complement of the shifted logic levels corresponding to A, B, C, D, or B.

As a further alternative the multiplane switches may use reed relay contacts which are capable of being switched into the 10 required conditions, one advantage of this being the ease with which the switch arrangement can be controlled from a distance.

The second arrangement will now be described. The main difference as compared with the first arrangement is that the second arrangement operates to subtract one number from another; the general principle of the operation is however the same. Like the first arrangement it is particularly, but by no means exclusively, suitable for use in an absolute system of measurement for angular or linear displacement using decimal notation.

The combinations which arise when differencing two numbets are indicated in FIG. 10 which corresponds to FIG. 1. A negative carry is required for all resultants below the diagonal line.

Adopting the same notation as previously, the requirements for a negative carry (or borrow) may be summarized as follows:

A negative carry is required for all n,-n,, 0, which may be expressed:

n,$ 4; -9s n, (all combinations) (4) PK). 11, to which reference is now made shows the way in which the negative carry is implemented. Each of the inputs, for example the input terminal 70 corresponding to digit 1, is connected to a pair of two-input AND-gates 71 and 72. The other inputs of the gates 71 and 72 are connected to a no carry line 73 and a carry line 74 respectively, the lines 73 and 74 being connected to the preceding decade. The output of the gate 71 is connected to a tenninal 75 which forms the digit 0 input terminal for the IO-condition switch, and the output of the gate 72 is connected to the terminal 76 which forms the digit 1 input terminal for the lO-condition switch. Thus a signal applied to the terminal 70 will result in an output signal at the terminal 76 if there is no carry and an output at the terminal 75 if there is a carry.

FIGS. 12 and 13 show logic arrangements for providing carry signals for the cases covered by expressions (4) and (5) above. An arrangement similar to that shown in FIG. 13 is required for the cases covered by expression (6) above. All these arrangements are generally similar in form and operation to those described above with reference to F lGS. 3 and 4 and will not therefore be described further here.

Reference will now be made to FIG. 14 which shows that part of the second arrangement which deals with one decade. The form and operation is closely similar to the corresponding part of the first arrangement described above with reference to FIG. 5 and it will not therefore be described in detail except in one respect. This relates to the means for implementing jump carries.

ln the second arrangement the conditions which necessitate the implementation of a jump carry at the input to one decade are that the preceding decade must have an input to the terminal of the switch corresponding to digit 9 and a carry signal at the output of the next preceding decade.

Various modifications can be made to the second arrangement, for example those described above with reference to the first arrangement.

I claim:

1. An arrangement for adding together two n-digit decimal numbers, comprising:

l. for each decade of the numbers except that corresponding to the least significant digit; first means to add one to the input digit to the decade if a carry signal is being supplied from the immediately preceding decade, 2. for each decade of the numbers;

second means to shift the input digit (after the addition of the carry ifany) to a value equal to the least significant digit of the number obtained by summing the input digit (after the addition of the carry if any) and the digit to be added, the second means comprising a lO-condition multiplane switch means, the 10 conditions of the switch means corresponding respectively to digits in the range 0 to 9 to be added, and the switch means having a first plurality of planes wired to perform said shift of the input digit and a second plurality of planes wired so as to cooperate with associated logic means to generate a carry signal for the immediately succeeding decade when said addition or shift makes such a carry necessary, the wiring of said second plurality of planes and said cooperation with said logic means being such that the values of the input digit (after the addition of the carry if any) and of the digit to be added are tested to determine whether said values satisfy any one of a plurality of different conditions, which conditions, which conditions together define all of the combinations of said values for which a carry to the immediately succeeding decade is necessary, and

3. for all the decades of numbers in common;

third means to generate a carry signal for the second suc cecding decade when a carry signal is being generated for the immediately succeeding decade and the input digit to the immediately succeeding decade is 9.

2. An arrangement according to claim 1, wherein said first means comprises two two-input AND-gates for each input digit; and for each input digit, means to supply input signals to one of the inputs of each of the two gates appropriate to that input digit when the input digit is present, means to supply an input signal to the other input of one said gate when no carry signal is being supplied from the immediately preceding decade whereby said gate supplies an output signal corresponding to said input digit, and means to supply an input signal to the other input of the other said gate when a carry signal is being supplied from the immediately preceding decade whereby the other said gate supplies an output signal corresponding to the digit next above said input digit.

3. An arrangement according to claim 1 wherein said first plurality is 10 and said second plurality is 5.

4. An arrangement according to claim 1 wherein said switch means is a, 15-plane, mechanically operated switch, having one movable contact per plane these 15 contacts being ganged together.

5. An arrangement according to claim 1 wherein one of said decimal numbers is coded.

6. An arrangement according to claim 5 wherein each digit of said decimal number is represented by two signals out of a possible five being in one or other of two conditions.

7. An arrangement according to claim 6 wherein said first means comprises five-way two-condition switch means, the condition of which is determined by the presence or absence of a carry signal from the preceding decade, and means to invert the condition of one of the input signals.

8. An arrangement according to claim 1 wherein said input digit (after the addition of the carry if any) is n, and said digit to be added is n and said plurality of different conditions are:

0 3 n 4; 6 3 n 9; (appropriate combinations) 5 Sn,$9; 5Sn S9; (all combinations) 5 S n, 9; l S n S 4; (appropriate combinations).

9. An arrangement for subtracting one n-digit decimal number from another comprising:

1. for each decade of the numbers except that corresponding to the least significant digit; first means to subtract one from the input digit to the decade if a borrow signal is being supplied from the immediately preceding decade, 2. for each decade of the numbers; I second means to shift the input digit (after the subtraction of the borrow if any) to a value equal to the least significant digit of the number obtained by differencing the input digit (after the subtraction of the borrow if any) and the digit to be subtracted, the second means comprising a l0-condition multiplane switch means, the 10 conditions of the switch means corresponding respectively to digits in the range 0 to 9 to be subtracted, and the switch means having a first plurality of planes wired to perform said shift of the input digit and a second plurality of planes wired so as to cooperate with associated logic means to generate a borrow signal for the immediately succeeding decade when said subtraction or shift makes such a borrow necessary, the wiring of said second plurality of planes and said cooperation with the associated logic means being such that the values of the input digit (after the subtraction of the borrow if any) and of the digit to be subtracted are tested to determine whether said values satisfy any one of a plurality of different conditions, which conditions together define all of the combinations of said values for which a borrow from the immediately succeeding decade is necessary, and 3. for all the decades of the numbers in common;

third means to generate a borrow signal for the second succeeding decade when a borrow signal is being generated for the immediately succeeding decade and the input digit to the immediately succeeding digit is 9.

10. An arrangement according to claim 9 wherein said input digit (after the subtraction of the borrow if any) is n, and said digit to be subtracted is n,, said plurality of different conditions are:

n, 54; 9 su s 5 (all combinations) 0 5 n, 53; -4 n, 5 l (appropriate combinations) 5 $8; -95 n, -'6; (appropriate combinations).

II. An arrangement according to claim 9 wherein said first plurality is l0 and said second plurality is five 12. An arrangement according to claim 9 wherein said switch means is a fifteenplane, mechanically operated switch, having one movable contact per plane these fifteen contacts being ganged together.

13. An arrangement according to claim 9 wherein one of said decimal numbers is coded.

14. An arrangement according to claim 13 wherein said first means comprises two two-input AND-gates for each input digit; and for each input digit, means to supply input signals to one of the inputs of each of the two gates appropriate to that input digit when that input digit is present, means to supply an input signal to the other input of one said gate when no borrow signal is being supplied from the immediately preceding decade whereby said gate supplies an output signal corresponding to said input digit, and means to supply an input signal to the other input of the other said gate when a borrow signal is being supplied from the immediately preceding decade whereby the other said gate supplies an output signal corresponding to the digit next below said input digit.

15. An arrangement according to claim 13 wherein each digit of said decimal number is represented by two signals out I of a possible five being in one or other of two conditions.

l6. An arrangement according to claim 15 wherein said first means comprises five-way two-condition switch means, the condition of which is determined by the presence or absence of a carry signal from the preceding decade, and means to invert the condition of one of the input signals. 

1. An arrangement for adding together two n-digit decimal numbers, comprising:
 1. for each decade of the numbers except that corresponding to the least significant digit; first means to add one to the input digit to the decade if a carry signal is being supplied from the immediately preceding decade,
 2. for each decade of the numbers; second means to shift the input digit (after the addition of the carry if any) to a value equal to the least significant digit of the number obtained by summing the input digit (after the addition of the carry if any) and the digit to be added, the second means comprising a 10-condition multiplane switch means, the 10 conditions of the switch means corresponding respectively to digits In the range 0 to 9 to be added, and the switch means having a first plurality of planes wired to perform said shift of the input digit and a second plurality of planes wired so as to cooperate with associated logic means to generate a carry signal for the immediately succeeding decade when said addition or shift makes such a carry necessary, the wiring of said second plurality of planes and said cooperation with said logic means being such that the values of the input digit (after the addition of the carry if any) and of the digit to be added are tested to determine whether said values satisfy any one of a plurality of different conditions, which conditions, which conditions together define all of the combinations of said values for which a carry to the immediately succeeding decade is necessary, and
 3. for all the decades of numbers in common; third means to generate a carry signal for the second succeeding decade when a carry signal is being generated for the immediately succeeding decade and the input digit to the immediately succeeding decade is
 9. 2. for each decade of the numbers; second means to shift the input digit (after the addition of the carry if any) to a value equal to the least significant digit of the number obtained by summing the input digit (after the addition of the carry if any) and the digit to be added, the second means comprising a 10-condition multiplane switch means, the 10 conditions of the switch means corresponding respectively to digits In the range 0 to 9 to be added, and the switch means having a first plurality of planes wired to perform said shift of the input digit and a second plurality of planes wired so as to cooperate with associated logic means to generate a carry signal for the immediately succeeding decade when said addition or shift makes such a carry necessary, the wiring of said second plurality of planes and said cooperation with said logic means being such that the values of the input digit (after the addition of the carry if any) and of the digit to be added are tested to determine whether said values satisfy any one of a plurality of different conditions, which conditions, which conditions together define all of the combinations of said values for which a carry to the immediately succeeding decade is necessary, and
 2. An arrangement according to claim 1, wherein said first means comprises two two-input AND-gates for each input digit; and for each input digit, means to supply input signals to one of the inputs of each of the two gates appropriate to that input digit when the input digit is present, means to supply an input signal to the other input of one said gate when no carry signal is being supplied from the immediately preceding decade whereby said gate supplies an output signal corresponding to said input digit, and means to supply an input signal to the other input of the other said gate when a carry signal is being supplied from the immediately preceding decade whereby the other said gate supplies an output signal corresponding to the digit next above said input digit.
 2. for each decade of the numbers; second means to shift the input digit (after the subtraction of the borrow if any) to a value equal to the least significant digit of the number obtained by differencing the input digit (after the subtraction of the borrow if any) and the digit to be subtracted, the second means comprising a 10-condition multiplane switch means, the 10 conditions of the switch means corresponding respectively to digits in the range 0 to 9 to be subtracted, and the switch means having a first plurality of planes wired to perform said shift of the input digit and a second plurality of planes wired so as to cooperate with associated logic means to generate a borrow signal for the immediately succeeding decade when said subtraction or shift makes such a borrow necessary, the wiring of said second plurality of planes and said cooperation with the associated logic means being such that the values of the input digit (after the subtraction of the borrow if any) and of the digit to be subtracted are tested to determine whether said values satisfy any one of a plurality of different conditions, which conditions together define all of the combinations of said values for which a borrow from the immediately succeeding decade is necessary, and
 3. for all the decades of numbers in common; third means to generate a carry signal for the second succeeding decade when a carry signal is being generated for the immediately succeeding decade and the input digit to the immediately succeeding decade is
 9. 3. An arrangement according to claim 1 wherein said first plurality is 10 and said second plurality is
 5. 3. for all the decades of the numbers in common; third means to generate a borrow signal for the second succeeding decade when a borrow signal is being generated for the immediately succeeding decade and the input digit to the immediately succeeding digit is
 9. 4. An arrangement according to claim 1 wherein said switch means is a, 15-plane, mechanically operated switch, having one movable contact per plane these 15 contacts being ganged together.
 5. An arrangement according to claim 1 wherein one of said decimal numbers is coded.
 6. An arrangement according to claim 5 wherein each digit of said decimal number is represented by two signals out of a possible five being in one or other of two conditions.
 7. An arrangement according to claim 6 wherein said first means comprises five-way two-condition switch means, the condition of which is determined by the presence or absence of a carry signal from the preceding decade, and means to invert the condition of one of the input signals.
 8. An arrangement according to claim 1 wherein said input digit (after the addition of the carry if any) is nx and said digit to be added is nc, and said plurality of different conditions are: 0 nx 4; 6 no 9; (appropriate combinations) 5 nx 9; 5 no 9; (all combinations) 5 nx 9; 1 no 4; (appropriate combinations).
 9. An arrangement for subtracting one n-digit decimal number from another comprising:
 10. An arrangement according to claim 9 wherein said input digit (after the subtraction of the borrow if any) is nx and said digit to be subtracted is no, said plurality of different conditions are: 0 nx 4; -9 no -5 (all combinations) 0'' nx 3; -4 no -1; (appropriate combinations) 5 nx 8; -9 no -6; (appropriate combinations).
 11. An arrangement according to claim 9 wherein said first plurality is 10 and said second plurality is five.
 12. An arrangement according to claim 9 wherein said switch means is a fifteen-plane, mechanically operated switch, having one movable contact per plane these fifteen contacts being ganged together.
 13. An arrangement according to claim 9 wherein one of said decimal numbers is coded.
 14. An arrangement according to claim 13 wherein said first means comprises two two-input AND-gates for each input digit; and for each input digit, means to supply input signals to one of the inputs of each of the two gates appropriate to that input digit when that input digit is present, means to supply an input signal to the other input of one said gate when no borrow signal is being supplied from the immediately preceding decade whereby said gate supplies an output signal corresponding to said input digit, and means to supply an input signal to the other input of the other said gate when a borrow signal is being supplied from the immediately preceding decade whereby the other said gate supplies an output signal corresponding to the digit next below said input digit.
 15. An arrangement according to claim 13 wherein each digit of said decimal number is represented by two signals out of a possible five being in one or other of two conditions.
 16. An arrangement according to claim 15 wherein said first means comprises five-way two-condition switch means, the condition of which is determined by the presence or absence of a carry signal from the preceding decade, and means to invert the condition of one of the input signals. 